Advantest expands its SiConic test platform to include DFT engineering capabilities, aiming to speed up production‑ready chip test development
Executive summary: Advantest extended its SiConic® test ecosystem to incorporate DFT engineering tools, as stated in a GlobeNewswire press release. By adding DFT capabilities, Advantest seeks to shorten the test development cycle for chip manufacturers, which could improve time‑to‑market and lower engineering costs.
Who is involved: Advantest (the test equipment provider) and its SiConic® platform users, primarily semiconductor companies and DFT engineers.
Likely next: Advantest may roll out the DFT engineering module to existing SiConic customers in the coming quarters, with potential follow‑up announcements detailing adoption metrics.
Advantest announced on July 16 2026 that its SiConic® test platform now incorporates design‑for‑test (DFT) engineering capabilities. According to the company’s press release, the extension adds DFT workflows directly into the SiConic ecosystem, a change the firm says is intended to accelerate the creation of production‑ready test programs for semiconductors. By integrating DFT engineering into a platform that already handles test execution and data analysis, Advantest aims to reduce the number of separate steps required to move from chip design to a ready‑to‑use test solution. This consolidation could help semiconductor manufacturers shorten test‑development cycles, which is increasingly important as device complexity grows and time‑to‑market pressures mount. The move signals Advantest’s effort to broaden the functional scope of its SiConic offering in response to industry demand for more unified test‑development tools. While the full market impact will depend on how quickly customers adopt the new capabilities, the announcement positions the company to address a recognized bottleneck in the semiconductor test flow.
Timeline
- — Advantest Extends SiConic® Ecosystem to DFT Engineering, Accelerating Production-Ready Test Development (GlobeNewswire)
Analysis — what this means
Sectors affected
- Semiconductor test equipment
- Design‑for‑Test engineering tools
Key entities
Sources
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